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Product Specification
PE3341
Product Description
The PE3341 is a high performance integer-N PLL with embedded EEPROM capable of frequency synthesis up to 2700 MHz with a speed-grade option to 3000 MHz. The EEPROM allows designers to permanently store control bits, allowing easy configuration of self-starting synthesizers. The superior phase noise performance of the PE3341 is ideal for applications such as sonet, wireless base stations, fixed wireless, and RF instrumentation systems. The PE3341 features a /10/11 dual modulus prescaler, counters, a phase comparator, and a charge pump as shown in Figure 1. Counter values are programmable through a threewire serial interface. The PE3341 UltraCMOSTM Phase Locked-Loop is manufactured in Peregrine's patented Ultra Thin Silicon (UTSi(R)) CMOS process, offering excellent RF performance with the economy and integration of conventional CMOS.
2700 MHz Integer-N PLL with Field-Programmable EEPROM
Features
* Field-programmable EEPROM for self-
starting applications
* Standard 2700 MHz operation,
3000 MHz speed-grade option * /10/11 dual modulus prescaler
* Internal charge pump * Serial programmable * Low power -- 20 mA at 3 V * Ultra-low phase noise * Available in 24-lead TSSOP or 20-lead
4x4 mm QFN package
Figure 1. Block Diagram
Fin Fin ENH E_WR Data Clock
Serial Interface Mux Enhancement Register (8-bit) Primary Register (20-bit) EE Register (20-bit)
Prescaler /10/11
M Counter /2 to /512
13
20
Secondary Register (20-bit)
PD_U Phase Detector Charge Pump PD_D
CP
20 6
20 EELoad
Transfer Logic
LD 2k 6 Cext
VPP S_WR fr EESel FSel
EEPROM R Counter /1 to /64
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PE3341
Product Specification
Figure 2. Pin Configurations (Top View)
VDD GND ENH S_WR Data Clock GND FSel E_WR
1 2 3 4 5 6 24 23 22 21 20 19
Figure 3. Package Types
24-lead TSSOP, 20-lead QFN
fr
EESel
17
GND
ENH fr
18
20
19
N/C CP VDD Dout LD EELoad Cext GND Fin
S_WR Data Clock FSel E_WR
1 2 3 4 5
16
NC
EESel
VDD
15
CP VDD Dout LD EELoad
24-lead TSSOP
7 8 9 18 17 16 15 14 13
20-lead QFN 4x4 mm
Exposed Solder Pad (Bottom Side)
14 13 12 11
VPP
FIN
VDD
FIN
VPP 10 VDD 11 Fin 12
Table 2. Pin Descriptions
Pin No. TSSOP
1 2 3 20
Pin No. QFN
19
Pin Name
VDD GND ENH
Type
(Note 1) (Note 2) Input
CEXT
10
6
7
8
9
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required. Ground. Enhancement mode control line. When asserted LOW, enhancement register bits are functional. Internal 70 k pull-up resistor. Secondary Register WRITE input. Primary Register contents are copied to the Secondary Register on S_WR rising edge. Also used to control Serial Port operation and EEPROM programming. Binary serial data input. Input data entered LSB (B0) first. Serial clock input. Data is clocked serially into the 20-bit Primary Register, the 20-bit EE Register, or the 8-bit Enhancement Register on the rising edge of Clock. Also used to clock EE Register data out Dout port. Ground. Frequency Register selection control line. Internal 70 k pull-down resistor. Enhancement Register write enable. Also functions as a Serial Port control line. Internal 70 k pull-down resistor. EEPROM erase/write programming voltage supply pin. Requires a 100pF bypass capacitor connected to GND. Same as pin 1. Prescaler input from the VCO. Prescaler complementary input. A series 50 resistor and DC blocking capacitor should be placed as close as possible to this pin and connected to the ground plane. Ground. Logical "NAND" of PD_U and PD_D terminated through an on-chip, 2 k series resistor. Connecting CEXT to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. Control line for Serial Data Port, Frequency Register selection, EE Register parallel loading, and EEPROM programming. Internal 70 k pull-down resistor. Lock detect output, an open-drain logical inversion of C EXT. When the loop is in lock, LD is high impedance; otherwise, LD is a logic LOW.
4 5 6 7 8 9 10 11 12 13 14 15 16 17
1 2 3
S_WR Data Clock GND
Input Input Input (Note 2) Input Input Input (Note 1) Input Input (Note 2) Output Input Output, OD
4 5 6 7 8 9
FSel E_WR VPP VDD Fin Fin GND
10 11 12
CEXT EELoad LD
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Document No. 70-0053-04 UltraCMOSTM RFIC Solutions
PE3341
Product Specification
Pin No. TSSOP
18 19 20 21 22 23 24
Pin No. QFN
13 14 15 16 17
Pin Name
Dout VDD CP N/C EESel GND
Type
Output (Note 1) Output ENH. Same as pin 1.
Description
Data out function. Dout is defined with the Enhancement Register and enabled with
Charge pump output. Sources current is when fc leads fp and sinks current when fc lags fp. No connection. Control line for Frequency Register selection, EE Register parallel loading, and EEPROM programming. Internal 70 k pull-up resistor. Ground. Reference frequency input.
Input (Note 2) Input
18
fr
Notes 1: V DD pins 1, 11, and 19 (TSSOP) or pins 6, 14 and 19 (QFN), are connected by diodes and must be supplied with the same positive voltage level. 2: Ground connections are made through the exposed solder pad. The solder pad must be soldered to the ground plane for proper operation.
Table 2. Absolute Maximum Ratings
Symbol
VDD VI TStg
Table 4. ESD Ratings
Units
V V C
Parameter/Conditions
Supply voltage Voltage on any digital input Storage temperature range
Min
-0.3 -0.3 -65
Max
+4.0 VDD+0.3 +85
Symbol
VESD VESD (VPP)
Parameter/Conditions
ESD voltage human body model (Note 1) ESD voltage human body model (Note 1)
Min
Max
1000 200
Units
V V
Note 1: Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2
Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC and AC Characteristics table. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 3. DC Electrical Specifications
Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating in Table 4. Latch-Up Avoidance
Symbol
VDD TA
Parameter/Conditions
Supply voltage Operating ambient temperature range
Min
2.85 -40
Max
3.15 85
Units
V C
Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up.
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PE3341
Product Specification
Table 5. DC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified
Symbol
IDD Digital Inputs: S_WR, Data, Clock VIH VIL IIH IIL High-level input voltage Low-level input voltage High-level input current Low-level input current VDD = 2.85 to 3.15 V VDD = 2.85 to 3.15 V VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V -1 0.7 x VDD 0.3 x VDD +1 V V A A
Parameter
Operational supply current; Prescaler enabled
Conditions
VDD = 2.85 to 3.15 V
Min
Typ
20
Max
30
Units
mA
Digital inputs: ENH, EESel (contains a 70 k pull-up resistor) VIH VIL IIH IIL High-level input voltage Low-level input voltage High-level input current Low-level input current VDD = 2.85 to 3.15 V VDD = 2.85 to 3.15 V VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V -100 0.7 x VDD 0.3 x VDD +1 V V A A
Digital inputs: FSel, EELoad, E_WR (contains a 70 k pull-down resistor) VIH VIL IIH IIL High-level input voltage Low-level input voltage High-level input current Low-level input current VDD = 2.85 to 3.15 V VDD = 2.85 to 3.15 V VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V -1 0.7 x VDD 0.3 x VDD +100 V V A A
EE Memory Programming Voltage and Current: VPP, IPP VPP_WRITE VPP_ERASE IPP_WRITE IPP_ERASE EEPROM write voltage EEPROM erase voltage EEPROM write cycle current EEPROM erase cycle current -10 12.5 -8.5 30 V V mA mA
Reference Divider input: fr IIHR IILR High-level input current Low-level input current VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V -100 +100 A A
Counter output: Dout VOLD VOHD Output voltage LOW Output voltage HIGH Iout = 6 mA Iout = -3 mA VDD - 0.4 0.4 V V
Lock detect outputs: (CEXT, LD) VOLC VOHC VOLLD Output voltage LOW, CEXT Output voltage HIGH, CEXT Output voltage LOW, LD Iout = 0.1 mA Iout = -0.1 mA Iout = 1 mA VDD - 0.4 0.4 0.4 V V V
Charge Pump output: CP ICP - Source ICP - Sink ICPL ICP - Source VS. ICP - Sink ICP VS. VCP Drive current Drive current Leakage current Sink vs. source mismatch Output current magnitude variation vs. voltage VCP = VDD / 2 VCP = VDD / 2 1.0 V < VCP < VDD - 1.0 V VCP = VDD / 2, TA = 25 C 1.0 V < VCP < VDD - 1.0 V TA = 25 C (c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 17 Document No. 70-0053-04 UltraCMOSTM RFIC Solutions -2.6 1.4 -1 -2 2 -1.4 2.6 1 15 15 mA mA A % %
PE3341
Product Specification
Table 6. AC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified
Symbol
fClk tClkH tClkL tDSU tDHLD tPW tCWR tCE tWRC tEC tEESU tEEPW tVPP
Parameter
Serial data clock frequency Serial clock HIGH time Serial clock LOW time Data set-up time to Clock rising edge Data hold time after Clock rising edge S_WR pulse width Clock rising edge to S_WR rising edge Clock falling edge to E_WR transition S_WR falling edge to Clock rising edge E_WR transition to Clock rising edge (Note 1)
Conditions
Min
Max
10
Units
MHz ns ns ns ns ns ns ns ns ns ns
Control Interface and Registers (see Figure 4)
30 30 10 10 30 30 30 30 30
EEPROM Erase/Write Programming (see Figures 5 & 6) EELoad rising edge to VPP rising edge VPP pulse width VPP pulse rise and fall times (Note 2) 500 25 1 30 ms s
Main Divider (Including Prescaler) FIn FIn PFIn Operating frequency Operating frequency Input level range Speed-grade option (Note 3) External AC coupling 300 300 -5 2700 3000 5 MHz MHz dBm
Main Divider (Prescaler Bypassed) FIn PFIn Operating frequency Input level range (Note 4) External AC coupling (Note 4) 50 -5 270 5 MHz dBm
Reference Divider fr Pfr Phase Detector fc Comparison frequency (Note 6) 20 MHz Operating frequency Reference input power (Note 4) (Note 5) Single ended input -2 100 MHz dBm
SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, V DD = 3.0 V, Temp = -40 C) 100 Hz Offset 1 kHz Offset Note 1: Note 2: Note 3: Note 4: -75 -85 dBc/Hz dBc/Hz
fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fClk specification. Rise and fall times of the VPP programming voltage pulse must be greater than 1 s. The maximum frequency of operation can be extended to 3.0 GHz by ordering a special speed-grade option. Please refer to Table 14, Ordering Information, for ordering details. CMOS logic levels can be used to drive FIn input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum frequency limit exists when operated in this mode. CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. Parameter is guaranteed through characterization only and is not tested.
Note 5: Note 6:
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PE3341
Product Specification
Functional Description The PE3341 consists of a dual modulus prescaler, three programmable counters, a phase detector with charge pump and control logic with EEPROM memory (see Figure 1). The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the state of the internal modulus select logic. The R and M counters divide the reference and prescaler outputs by integer values stored in one of three selectable registers. The modulus select logic uses the 4-bit A counter. The phase-frequency detector generates up and down frequency control signals that direct the charge pump operation, and are also used to enable a lock detect circuit. Frequency control data is loaded into the device via the Serial Data Port, and can be placed in three separate frequency registers. One of these registers (EE register) is used to load from and write to the non-volatile 20-bit EEPROM. Various operational and test modes are available through the enhancement register, which is only accessible through the Serial Data Port (it cannot be loaded from the EEPROM). Main Counter Chain The main counter chain divides the RF input frequency, Fin, by an integer derived from the user-defined values in the M and A counters. It operates in two modes: High Frequency Mode Setting PB (prescaler bypass) LOW enables the /10/11 prescaler, providing operation to 2.7 GHz. In this mode, the output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation:
fp = Fin / [10 x (M + 1) + A] where 0 A 15 and A M + 1; 1 M 511 (1)
A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. Programming the M counter with the minimum value of 1 will result in a minimum M counter divide ratio of 2. Programming the M and A counters with their maximum values provides a divide ratio of 5135. Prescaler Bypass Mode Setting the PB bit of a frequency register HIGH allows Fin to bypass the /10/11 prescaler. In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. The following equation relates Fin to the reference frequency fr:
Fin = (M + 1) x (fr / (R+1)) where 1 M 511 (3)
Reference Counter The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation:
fc = fr / (R + 1) where 0 R 63 (4)
Note that programming R with 0 will pass the reference frequency, fr, directly to the phase detector. Phase Detector and Charge Pump The phase detector is triggered by rising edges from the main counter (fp) and the reference counter (fc). It has two outputs, PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses LOW. If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses LOW. The width of either pulse is directly proportional to the phase offset between the fp and fc signals. The signals from the phase detector are also routed to an internal charge pump. PD_U controls a current source at pin CP, and PD_D controls a current sink at pin CP. When using a positive Kv VCO, PD_U pulses (current source) will increase the VCO frequency, and PD_D pulses (current sink) will decrease VCO frequency.
Document No. 70-0053-04 UltraCMOSTM RFIC Solutions
When the loop is locked, Fin is related to the reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1)) where 0 A 15 and A M + 1; 1 M 511 (2)
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PE3341
Product Specification
Lock Detect Output A lock detect signal is provided at pin LD, via the pin CEXT (see Figure 1). CEXT is the logical "NAND" of PD_U and PD_D waveforms, driven through a series 2k ohm resistor. When the loop is locked, this output will be HIGH with narrow pulses LOW. Connecting CEXT to an external shunt capacitor provides integration of this signal. The CEXT signal is sent to the LD pin through an internal inverting comparator with an open drain output. Thus LD is an "AND" function of PD_U and PD_D.
Serial Data Port The Serial Data Port allows control data to be entered into the device. This data can be directed into one of three registers: the Enhancement register, the Primary register, and the EE register. Table 7 defines the control line settings required to select one of these destinations. Input data presented on pin 5 (Data) is clocked serially into the designated register on the rising edge of Clock. Data is always loaded LSB (B0) first into the receiving register. Figure 4 defines the timing requirements for this process.
Table 7. Serial Interface
S_WR
0 0 0
E_WR
0 1 X
EELoad
0 0 1
Register Loaded
Primary Register Enhancement Register EE Register
Figure 4. Serial Interface Timing Diagram
Data
E_WR EELoad
tEC tCE
Clock
S_WR
tDSU tDHLD tClkH tClkL tCWR tPW tWRC
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PE3341
Product Specification
Frequency Registers There are three independent frequency registers, any one of which can be selected to control the operation of the device. Each register is 20 bits in length, and provides data to the three counters and the prescaler bypass control. Table 8 defines these bit assignments. Primary Register The Primary Register is a serial shift register, loaded through the Serial Data Port. It can be selected to control the PLL as shown in Table 9. It is not buffered, thus when this register is selected to control the PLL, its data is continuously presented to the counters during a load operation. This register is also used to perform a parallel load of data into the Secondary Register. Secondary Register The Secondary Register is a parallel-load register. Data is copied into this register from the Primary Register on the rising edge of S_WR, according to the timing diagrams shown in Figure 3. It can be selected to control the PLL as shown in Table 9.
EE Register The EE Register is a serial/parallel-in, serial/ parallel-out register, and provides the interface to the EEPROM. It is loaded from the Serial Data Port to provide the parallel data source when writing to the EEPROM. It also accepts stored data from the EEPROM for controlling the PLL. Serial loading of the EE Register is done as shown in Table 7 and Figure 4. Parallel loading of the register from EEPROM is accomplished as shown in Table 10. The EE register can be selected to control the PLL as shown in Table 9. Note that it cannot be selected to control the PLL using data that has been loaded serially. This is because it must first go through one of the two conditions in Table 10 that causes the EEPROM data to be copied into the EE Register. The effect of this is that only EEPROM data is used when the EE Register is selected. The contents of the EE register can also be shifted out serially through the Dout pin. This mode is enabled by appropriately programming the Enhancement Register. In this mode, data exits the register on the rising edge of Clock, LSB (B0) first, and is replaced with the data present on the Data input pin. Tables 7 and 12 define the settings required to enable this mode.
Table 8. Primary / Secondary / EE Register Bit Assignments
R5 B0 R4 B1 M8 B2 M7 B3 PB B4 M6 B5 M5 B6 M4 B7 M3 B8 M2 B9 M1 B10 M0 B11 R3 B12 R2 B13 R1 B14 R0 B15 A3 B16 A2 B17 A1 B18 A0 B19
Table 9. Frequency Register Selection
EESel
0 0 1
Table 10. EE Register Load from EEPROM
EESel
_ 1
FSel
1 0 X
EELoad
0 0 0
Register Selected
Primary Register Secondary Register EE Register
EELoad
0 \_
Function
EEPROM EE Register EEPROM EE Register
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Document No. 70-0053-04 UltraCMOSTM RFIC Solutions
PE3341
Product Specification
Enhancement Register The Enhancement Register is a buffered serial shift register, loaded from the Serial Data Port. It activates special test and operating modes in the PLL. The bit assignments for these modes are shown in Table 11. The functions of these Enhancement Register bits are shown in Table 12. A function becomes active when its corresponding bit is set HIGH. Note that bits 1, 2, 5, and 6 direct various data to the Dout pin, and for valid operation no more than one should be set HIGH simultaneously.
The Enhancement Register is buffered to prevent inadvertent control changes during serial loading. Data that has been loaded into the register is captured in the buffer and made available to the PLL on the falling edge of E_WR. A separate control line is provided to enable and disable the Enhancement mode. Functions are enabled by taking the ENH control line LOW. Note: The enhancement register bit values are unknown during power up. To avoid enabling the enhancement mode during power up, set the Enh pin high ("1") until the enhancement register bit values are programmed to a known state.
Table 11. Enhancement Register Bit Assignments
Reserved
B0
EE Register Output
B1
fp output
B2
Power down
B3
Counter load
B4
MSEL output
B5
fc output
B6
Reserved
B7
Table 12. Enhancement Register Functions
Bit Function
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Reserved EE Register Output fp output Power down Counter load MSEL output fc output Reserved Program to 0 Allows the contents of the EE Register to be serially shifted out Dout, LSB (B0) first. Data is shifted on rising edge of Clock. Provides the M counter output at Dout. Powers down all functions except programming interface. Immediate and continuous load of counter programming. Provides the internal dual modulus prescaler modulus select (MSEL) at Dout. Provides the R counter output at Dout. Program to 0
Description
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PE3341
Product Specification
EEPROM Programming Frequency control data that is present in the EE Register can be written to the non-volatile EEPROM. All 20 bits are written simultaneously in a parallel operation. The EEPROM is guaranteed for at least 100 erase/write cycles. Erase Cycle The EEPROM should be taken through an erase cycle before writing data, since the write operation performs a logical AND of the EEPROM's current contents with the data in the EE Register. Erasing the EEPROM is accomplished by holding the S_WR, EESel, and EELoad inputs HIGH, then applying one ERASE programming voltage pulse to the VPP input (see Table 13). The voltage source for this operation must be capable of supplying the EEPROM erase cycle current (IPP_ERASE, Table 5). The timing diagram is shown in Figure 5. Table 13. EEPROM Programming
S_WR
1 1
Write Cycle Using the Serial Data Port, the EE Register is first loaded with the desired data. The EEPROM is then programmed with this data by taking the S_WR input HIGH and EESel input LOW, then applying one WRITE programming voltage pulse to the VPP input. The voltage source for this operation must be capable of supplying the EEPROM write cycle current (IPP_WRITE, Table 5). The timing diagram of this operation is shown in Figure 6. Programming is completed by taking the EELoad input LOW. Note that it is possible to erroneously overwrite the EE Register with the EEPROM contents before the write cycle begins by unneeded manipulation of the EELoad bit (see Table 10).
EESel
1 0
EELoad
1 1
VPP
25ms @ -8.5V 25ms @ +12.5V
Function
Erase cycle Write cycle
Figure 5. EEPROM Erase Timing Diagram
EELoad S_WR EESel
tEESU
tVPP
tVPP
tEESU
0V
VPP_ERASE
tEEPW
8 5V
Figure 6. EEPROM Write Timing Diagram
EESel
0V
EELoad 3V
S_WR
tEESU tVPP tEEPW 12.5V tVPP tEESU
VPP_WRITE
0V
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Document No. 70-0053-04 UltraCMOSTM RFIC Solutions
PE3341
Product Specification
Gross EEPROM Programming Timing Grid Figure 7 shows a gross PE3341 EEPROM programming timing grid although each individual step has been described thoroughly in previous sections. It starts with EE Register load, and then together with other parameters a Vpp_ERASE negative pulse is applied to Vpp pin to erase the EEPROM contents and followed by a Vpp_WRITE pulse for EEPROM write cycle. The separation
between the Vpp_ERASE and Vpp_WRITE pulse has to be at least 100 ms if mechanical relays are used to avoid both being on at the same time. After EE programming, the contents of the EEPROM cells can be verified by setting Enhancement Register Bit 1. A procedure shown in Figure 8 is applied twice. The first time is to load the EE Register from EEPROM and the second time is to shift out the EE Register contents through Dout pin.
Figure 7. Gross PE3341 EEPROM Programming Timing Grid
>=100 ms
EELoad
3V 0V 3V
EESel
0V 3V
S_WR
0V 3V
E_WR
0V 3V
CHANNEL CODE
Data
ENH code sets Dout mux to EE
0V 3V
Clock
0V 3V
Dout
0V 0V
The final set of Dout is EEPROM content 25 ms 25 ms
Vpp_ERASE
-8.5V 12.5V
Vpp_WRITE
0V E E veri fy EE Register load EE PROM Erase Rough time scale 40 ms EE PROM Write EE Programming
Note: ENH/ ( Pin 3 in TSSOP or Pin 20 in QFN) is at low (0) for this process.
EE Register load from EEPROM
EE Register shifted out through Dout
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PE3341
Product Specification
Figure 8. Details of EE register contents loaded from EEPROM and then shifted out Serially through Dout pin - The procedure is performed twice.
EELoad
3V 0V 3V
EESel
0V
S_WR
0V 3V
E_WR
0V 3V
Data
0V 3V
Clock
0V
Dout
(example)
3V 0V Enhancement Register Programming EE Register load from EEPROM
0 1010011111000111001
EE Register shifted out through Dout Rough time scale
20 us
Note: ENH/ ( Pin 3 in TSSOP or Pin 20 in QFN) is at low (0) for this process.
In Figure 8, the first step is to program Enhancement Register to set Bit 1 high ("1") to access EE Register Output Bit Function. Subsequent action, which includes pulses, allows the existing EE Register contents to be shifted out the Dout pin and the EEPROM contents are loaded to the EE Register. Since the initial data existing in the EE Register could be anything, the data must be flushed out before clocking the
contents of the EEPROM register out. After the same procedures are duplicated, the Dout output is the EEPROM content. Note that only 19 Clock pulses are enough for the 20-bit EE Register because the first bit data is already present at Dout pin. Also ENH/ (Pin 3 in TSSOP or Pin 20 in QFN) is set to low ("0") to access the Enhancement mode.
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Document No. 70-0053-04 UltraCMOSTM RFIC Solutions
PE3341
Product Specification
Application Information The PE3341 has been designed to allow a selfstarting PLL synthesizer to be built, removing the need to have a micro-controller or other programming source load data into the device on power-up. It can be used as a remotely controllable PLL as well, since the EEPROM circuitry has been added to a complete PLL core (PE3339). The PE3341's EEPROM can be programmed incircuit, or prior to assembly using a socketed fixture. It can be reprogrammed a minimum of 100 times, but is not designed to support constant reprogramming of the EEPROM by an application. Self-Starting Mode In self-starting applications, the EE Register is used to control the device and must be selected per Table 9. Additionally, the contents of the EEPROM must be copied to the EE Register per Table 10, and device power must be stable for this transfer to be reliably accomplished. These requirements can be met by connecting a capacitor of 50pF-10uF (evaluation design uses 3.3uF) from the EESel pin to ground. The delay of the rising edge on EESel, created by the RC time constant of its 70k ohm internal pull-up resistor and the external capacitor, will allow device power to stabilize first, ensuring proper data transfer. This edge is adaptable by capacitor value selection. The Vcc applied to the IC must be settled first.
Evaluation and Programming Kit Support To provide easy evaluation of the PE3341 and to also enable programming of small evaluation quantities, Peregrine has developed complete evaluation kits and programming kits for the PE3341 EEPROM PLLs. Evaluation Kits The evaluation kits consist of an evaluation board and support software enabling the user to evaluate the full functionality of the part. The EEPROM can be loaded with user specified values and then placed in a self start-up mode. Please refer to Table 14, Ordering Information, for the specific order codes. Programming Kits The programming kits consist of a programming board and support software that enables the user to program small quantities of devices for prototype evaluation and for small pre-production runs. Please refer to Table 14, Ordering Information, for the specific order codes Large production quantities can be special programmed at Peregrine for an additional charge. Please contact Peregrine Sales for pricing and leadtime at sales@psemi.com.
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PE3341
Product Specification
Figure 9. Package Drawing
24-lead TSSOP
TOP VIEW 0.65BSC 24 23 22 21 20 19 18 17 16 15 14 13
3.20 2X
12o REF 0.20 R 0.90 MIN
4.40 0.10 O1.00 0.10 GAGE PLANE -B1 2 3 4 5 6 7 8 9 10 11 12 .20 C B A 0.25 12o REF
R 0.90 MIN 0o 8o +.15 0.60 -.10 1.0 REF
1.00
1.00
0.325
-A-
7.80 0.10
0.90 0.05
1.10 MAX -C0.10 C 0.10 0.30 MAX CBA 0.10 0.05 6.40 SIDE VIEW
FRONT VIEW
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 14 of 17
Document No. 70-0053-04 UltraCMOSTM RFIC Solutions
PE3341
Product Specification
Figure 10. Package Drawing
20-lead QFN
4.00 INDEX AREA 2.00 X 2.00 -B2.00
2.00 0.25 C -A0.10 C 0.08 C 0.020 0.20 REF EXPOSED PAD & TERMINAL PADS SEATING PLANE 0.90 4.00 -C2.00 TYP 0.50 TYP 0.55 2.00 1.00
5 11
0.435 0.18 1.00 EXPOSED PAD 0.23 1 0.10 CAB 2.00
1 15 20 16 6 10
0.435
0.18
4.00
DETAIL A
DETAIL A
2
1. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP. 2. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
Document No. 70-0053-04 www.psemi.com
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 15 of 17
PE3341
Product Specification
Table 14. Ordering Information
Order Code
3341-01 3341-02 3341-03 3341-04 3341-53 3341-54 3341-31 3341-32 3341-33 3341-34 3341-00 3341-05 3341-06 3341-07
Part Marking
PE3341 PE3341 PE3341 PE3341 PE3341 PE3341 PE3341 PE3341 PE3341 PE3341 PE3341-EK PE3341-EK PE3341-PK PE3341-PK
Description
PE3341-24TSSOP-62A PE3341-24TSSOP-2000C PE3341-20QFN4x4-92A PE3341-20QFN4x4-3000C PE3341G-20QFN4x4-92A PE3341G-20QFN4x4-3000C PE3341-24TSSOP-62A (3GHz grade) PE3341-24TSSOP-2000C (3GHz grade) PE3341-20QFN4x4-92A (3GHz grade) PE3341-20QFN4x4-3000C (3GHz grade) PE3341-24TSSOP-EK (TSSOP) PE3341-20QFN4x4-EK (QFN) PE3341-24TSSOP-PK (TSSOP) PE3341-20MLP4x4-PK (QFN)
Package
24-lead TSSOP 24-lead TSSOP 20-lead QFN 20-lead QFN Green 20-lead QFN Green 20-lead QFN 24-lead TSSOP 24-lead TSSOP 20-lead QFN 20-lead QFN Evaluation Kit Evaluation Kit Programming Kit Programming Kit
Shipping Method
62 units / Tube 2000 units / T&R 92 units / Tube 3000 units / T&R 92 units / Tube 3000 units / T&R 62 units / Tube 2000 units / T&R 92 units / Tube 3000 units / T&R 1 / Box 1 / Box 1 / Box 1 / Box
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 16 of 17
Document No. 70-0053-04 UltraCMOSTM RFIC Solutions
PE3341
Product Specification
Sales Offices
The Americas Peregrine Semiconductor Corporation
9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499
North Asia Pacific Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213
Europe Peregrine Semiconductor Europe
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Peregrine Semiconductor, Korea
#B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305
South Asia Pacific Peregrine Semiconductor, China
Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652
Space and Defense Products
Americas: Tel: 505-881-0438 Fax: 505-881-0443 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice).
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